This invention relates generally to the use of serial buses to communicate between devices, circuits, systems, boards or networks, and in particular to serial backplane buses. The invention is applicable to any environment where a serial communication bus is or may be used, including circuit boards, backplanes, integrated circuits, and systems.
In producing integrated circuits or circuit boards for systems, the use of a serial communication bus for test and debug is rapidly becoming a standard practice. The use of the serial bus allows the system, circuit board or integrated circuits to be tested and connections to be confirmed without the need for intrusive hardware or test probes. This is particularly important as packaging of the devices reaches higher densities and for multiple integrated circuits packaged on a single module, or for systems where the circuitry is not available for physical access for other reasons.
Industry has developed and continues to develop standard protocols for serial busses of this kind. The standards are necessary and desirable to insure that parts and boards acquired from various vendors will be able to communicate on a common bus. In general, the concepts of this invention apply to any type of serial bus. However, to clarify the description of the invention it will be described as being a feature added to a well understood and documented IEEE/ANSI standard serial bus designed for testing ICs at the board level, referred to as IEEE/ANSI standard 1149.1 or more commonly as the JTAG boundary scan standard.
The IEEE/ANSI 1149.1 standard describes a 4-wire serial bus that can be used to transmit serial data to and receive serial data from multiple ICs on a board. While the 1149.1 serial bus was originally developed to serially access ICs at the board level, it can also be used at the backplane level to serially access ICs on multiple boards.
The 1149.1 standard describes a 4-wire serial bus that can be used to transmit serial data between a serial bus master and slave device. While 1149.1 was developed to serially access ICs on a board, it can be used at the backplane level to serially access boards in a backplane. 1149.1 has two serial access configurations, referred to as xe2x80x9cringxe2x80x9d and xe2x80x9cstarxe2x80x9d, that can be used at the backplane level.
In a backplane 1149.1 ring configuration, all boards in the backplane directly receive the control outputs from a primary serial bus master (PSBM) and are daisy chained between the PSBM""s data output and data input. During scan operation, the PSBM outputs control scan data through all boards in the backplane, via its test data output (TDO) and test data input (TDI) bus connections. The problem associated with the ring configuration is that the scan operation only works if all the boards are included in the backplane and are operable to scan data from their TDI input to TDO output signals. If one of the boards is removed or has a fault, the PSBM will be unable to scan data through the backplane. Since the ring configuration does not allow access to remaining boards when one is removed or disabled, it does not fully meet the needs of a serial bus for backplane and large system applications.
In a backplane 1149.1 star configuration, all boards in the backplane directly receive the test clock (TCK) and TDI signals from the PSBM and output a TDO signal to the PSBM. Also each board receives a unique test mode select (TMS) signal from the PSBM. In the star configuration only one board is enabled at a time to be serially accessed by the PSBM. When a board is enabled, the TMS signal associated with that board will be active while all other TMS signals are inactive. The problem with the star configuration is that each board requires its own TMS signal. In a backplane with 100 boards, the PSBM would have to have 100 individually controllable TMS signals, and the backplane would have to have traces for each of the 100 TMS signals. Due to these requirements, star configurations are typically not considered for backplane applications.
Two IEEE serial bus standards, P1149.5 and P1394, are in development for use in system backplanes. Since these standards are being specifically designed for backplane applications, they appear to overcome the problems stated using the 1149.1 standard bus as a backplane bus. However, the protocols of these anticipated standards are different from the 1149.1 protocol and therefore methods must be defined to translate between them and 1149.1.
The IEEE P1149.5 standard working group is currently defining a module test and maintenance bus that can be used in system backplane environments. P1149.5 is a single master/multiple slave bus defined by a 5-wire interface. The P1149.5 bus master initiates a data transfer operation by transmitting a data packet to all slave devices. The data packet consists of an address and command section. The slave device with a matching address is enabled to respond to the command section of the data packet as described in the P1149.5 standard proposal.
Interfacing an P1149.5 bus into an 1149.1 bus environment requires new additional system hardware and software, and designers with a detailed understanding of both bus types. Therefore, in using P1149.5 to interface into an 1149.1 environment, an unnecessary complication is added to an otherwise simple serial access approach. Another problem is that the bandwidth of the 1149.1 serial data transfer will be adversely affected by the 1149.5 to 1149.1 protocol conversion process and hardware.
The IEEE P1394 standard working group is currently defining a 2-wire high-speed serial bus that can be used in either a cable or system backplane environment. The P1394 standard, unlike P1149.5, is not a single master/multiple slave type bus. In P1394, all devices (nodes) connected to the bus are considered to be of equal mastership. The fact that P1394 can operate on a 2-wire interface makes this bus attractive in newer 32-bit backplane standards where only two wires are reserved for serial communication. However, there are problems in using P1394 as a backplane test bus to access 1149.1 board environments.
First, P1394 is significantly more complex in operation than P1149.1, thus devices designed to translate between P1394 and 1149.1 may be costly. Second, P1394 is not a full time test bus, but rather it is a general purpose serial communication bus, and its primary purpose in a backplane environment is to act as a backup interface in the event the parallel interface between boards becomes disabled. While 1149.1 test access can be achieved via P1394, it will be available only during time slices when the bus is not handling functional operations. Thus on-line 1149.1 test bus access will be limited and must be coordinated with other transactions occurring on the P1394 bus. This will require additional hardware and software complexity.
Another method of achieving a backplane to board level interface is to extend the protocol defined in the 1149.1 standard. Such an approach has been described in a paper presented at the 1991 International Test Conference by D. Bhavsar, entitled xe2x80x9cAn Architecture for Extending the IEEE Standard 1149.1 Test Access Port to System Backplanesxe2x80x9d. The Bhavsar paper describes a method of extending the protocol of 1149.1 so it can be used to access an interface circuit residing between the backplane and board level 1149.1 buses. The interface circuit responds to 1149.1 protocol transmitted over the backplane bus to load an address. If the address matches the address of the interface circuit, the interface circuit is connected to the backplane. After the interface circuit is connected to the backplane, additional 1149.1 protocol is input to the interface circuit to connect the backplane and board level 1149.1 buses. Following this connection procedure, the board level 1149.1 bus can be controlled by the backplane 1149.1 bus. Bhavsar""s approach also has problems that limit its effectiveness as a general purpose 1149.1 bus backplane to board interface.
Bhavsar""s approach does not allow selecting one board, then selecting another board without first resetting the backplane and board level 1149.1 buses, by transitioning them into their test logic reset (TLRST) states. Entering the TLRST state causes test conditions setup in the ICs of a previously selected board to be lost due to the test reset action of the 1149.1 bus on the test access ports (TAPs) of the ICs.
Also, it is often desirable to select and initiate self-tests in a selected group of backplane boards. However, since the Bhavsar approach requires resetting the 1149.1 bus each time a new board is selected, it is impossible to self-test more than one board at a time, because resetting the bus aborts any previously initiated self-test.
Thus, a need exists for a simple, efficient and effective means to provide support for the use of an 1149.1 standard serial bus in a multipleboard backplane environment. The invention described herein meets this need.
Generally, and in one form of the invention, a backplane access approach which provides a method of using the 1149.1 bus at the backplane level without incurring the problems previously described is disclosed. Using this approach, it is envisioned that one homogeneous serial bus may be used throughout a system design, rather than translating between multiple serial bus types. Employing a common serial bus in system designs can simplify software and hardware engineering efforts, since only an understanding of one bus type is required.
In a first embodiment of the invention a circuit, called an addressable shadow port (ASP), and a protocol, called a shadow protocol, is described which provides a simple and efficient method of directly connecting 1149.1 backplane and board buses together. When the 1149.1 backplane bus is in either its run test/idle (RT/IDLE) or test logic reset (TLRST) states, the ASP circuit can be enabled, via the shadow protocol of the invention, to connect a target board""s 1149.1 serial bus up to the backplane 1149.1 serial bus. After the shadow protocol herein described has been used to connect the target board and backplane buses together, the protocol of the invention becomes inactive and becomes transparent to the operation of the 1149.1 bus protocol.
The use of the invention results in several improvements over the use of the 1149.1 standard in a system or backplane environment or the other prior art extension approaches in terms of the efficiency of data transfers, the ability to remove boards or support backplanes where not all slots are populated, the ability to keep the 1149.1 bus in the idle state when selecting and deselecting boards, and the advantageous use of the well understood 1149.1 serial bus without the need for additional bus design or translator circuitry to accomplish these improvements.
An additional embodiment is disclosed wherein a single board contains multiple 1149.1 scan paths, each coupled to the backplane serial bus by means of an individually addressable shadow port, for additional flexibility in scan path and testability design. Other preferred embodiments and enhancements are also disclosed.
Further embodiments extend the ASP circuit and protocol to allow the local serial bus to be selectively controlled by a remote serial bus master circuit or alternatively by a primary serial bus master located on the backplane serial bus. The ASP capabilities are extended to allow input and output of parallel data to a memory via the ASP and the primary serial bus master. The ASP circuit and protocol are further extended to allow interrupt, status and command information to be transferred between a remote serial bus master and a primary serial bus master, to support sophisticated commands and remote functions autonomously executed by the remote serial bus master.
The invention is then applied to hierarchically organized systems, wherein multiple backplane systems are linked together through networks coupled in a multiple level environment. The ASP capabilities are extended to allow the primary serial bus master to directly select and send and receive data and commands to any board within the hierarchy.
An additional embodiment is disclosed wherein the circuitry and protocol of the invention is adapted for use with the proposed two wire serial backplane busses being considered by some in industry. Modifications and enhancements to make the invention compatible with such a bus are described.